AD9279-65EBZ屬于開發(fā)板套件編程器的評估板-模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的AD9279-65EBZ評估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The AD9279 is designed for low cost, low power, small size, and ease of use for medical ultrasound and automotive radar. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC), and an I/Q demodulator with programmable phase rotation.

Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, and a maximum gain of up to 52 dB. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the LNA input SNR is roughly 94 dB. In CW Doppler mode, each LNA output drives an I/Q demod ulator that has independently programmable phase rotation with 16 phase settings.

Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface.

FEATURES

8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator

Low power: 141 mW per channel, TGC mode, 40 MSPS; 60 mW per channel, CW mode

10 mm × 10 mm, 144-ball CSP-BGA

TGC channel input-referred noise: 0.8 nV/√Hz, max gain

Flexible power-down modes

Fast recovery from low power standby mode: <2 μs

Overload recovery: <10 ns

Low noise preamplifier (LNA)

Input-referred noise: 0.75 nV/√Hz, gain = 21.3 dB

Programmable gain: 15.6 dB/17.9 dB/21.3 dB

0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p

Dual-mode active input impedance matching

Bandwidth (BW): >100 MHz

Variable gain amplifier (VGA)

Attenuator range: ?45 dB to 0 dB

Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB

Linear-in-dB gain control

Antialiasing filter (AAF)

Programmable second-order LPF from 8 MHz to 18 MHz

Programmable HPF

Analog-to-digital converter (ADC)

SNR: 70 dB, 12 bits up to 80 MSPS

Serial LVDS (ANSI-644, low power/reduced signal)

CW mode I/Q demodulator

Individual programmable phase rotation

Output dynamic range per channel: >160 dBc/√Hz

Output-referred SNR: 155 dBc/√Hz, 1 kHz offset, ?3 dBFS