AD7641屬于集成電路（IC）的模數(shù)轉換器（ADC）。由亞德諾半導體技術有限公司制造生產(chǎn)的AD7641模數(shù)轉換器（ADC）模數(shù)轉換器（ADC、A/D 或 A 轉 D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉換器數(shù)和架構（例如自適應增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD7960 is an 18-bit, 5 MSPS, charge redistribution successive approximation (SAR), analog-to-digital converter (ADC). The SAR architecture allows unmatched performance both in noise and in linearity. The AD7960 contains a low power, high speed, 18-bit sampling ADC, an internal conversion clock, and an internal reference buffer. On the CNV± edge, the AD7960 samples the voltage difference between the IN+ and IN? pins.

FEATURES

Throughput: 5 MSPS

18-bit resolution with no missing codes

Excellent ac and dc performance

Dynamic range: 100 dB

SNR: 99 dB

THD: ?117 dB

INL: ±0.8 LSB (typical), ±2 LSB (maximum)

DNL: ±0.5 LSB (typical), ±0.99 LSB (maximum)

True differential analog input voltage range: ±4.096 V or ±5 V

Low power dissipation

46.5 mW at 5 MSPS with external reference buffer

(echoed clock mode)

64.5 mW at 5 MSPS with internal reference buffer

(echoed clock mode)

39 mW at 5 MSPS with external reference buffer

(self clocked mode, CNV± in CMOS mode)

SAR architecture

No latency/pipeline delay

External reference options: 2.048 V buffered to 4.096 V (internal

reference buffer), 4.096 V, and 5 V

Serial LVDS interface

Self clocked mode

Echoed clock mode

LVDS or CMOS option for conversion control (CNV± signal)

Operating temperature range of ?40°C to +85°C

32-lead, 5 mm × 5 mm LFCSP (QFN)

APPLICATIONS

Digital imaging systems

Digital X-rays

Computed tomography

IR cameras

MRI gradient control

High speed data acquisition

Spectroscopy

Test equipment