AD6655屬于開發(fā)板套件編程器的射頻評(píng)估開發(fā)套件開發(fā)板。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6655射頻評(píng)估和開發(fā)套件，開發(fā)板本系列中的產(chǎn)品適用于在已知實(shí)施環(huán)境中，提供能訪問射頻相關(guān)器件的功能或者有助于訪問該功能。所含的焦點(diǎn)產(chǎn)品范圍從射頻信號(hào)鏈元器件（如放大器和檢測(cè)器）到模塊化收發(fā)器，以及不直接包含焦點(diǎn)產(chǎn)品的適配器硬件，但此類硬件可供方便地訪問用戶單獨(dú)提供的特定射頻產(chǎn)品或系列。

GENERAL DESCRIPTION

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.

FEATURES

SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at 70 MHz @ 150 MSPS

SFDR = 80 dBc to 70 MHz @ 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply

Integer 1-to-8 input clock divider

Integrated dual-channel ADC

Sample rates up to 150 MSPS

IF sampling frequencies to 450 MHz

Internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Integrated wideband digital downconverter (DDC)

32-bit complex, numerically controlled oscillator (NCO)

Decimating half-band filter and FIR filter

Supports real and complex output modes

Fast attack/threshold detect bits

Composite signal monitor

Energy-saving power-down modes