AD6641BCPZ-500屬于RF/IF射頻/中頻RFID的RFIC模塊。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6641BCPZ-500RF 其它 IC 和模塊RF 其它 IC 和模塊產(chǎn)品系列包含各種獨(dú)特、專門或特定用途的產(chǎn)品，可與 RF、IF 和微波無線電應(yīng)用結(jié)合使用。示例包括 AM/FM 調(diào)諧器和接收器、偏置網(wǎng)絡(luò)、基帶處理器、計(jì)數(shù)器、數(shù)字可調(diào)電容器、下變頻器、倍頻器、移相器、前置分頻器、端接器、上變頻器、VCO 等。

GENERAL DESCRIPTION

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.

FEATURES

SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS

ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (?1.0 dBFS)

SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (?1.0 dBFS)

Excellent linearity

DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical

Integrated 16k × 12 FIFO

FIFO readback options

12-bit parallel CMOS at 62.5 MHz

6-bit DDR LVDS interface

SPORT at 62.5 MHz

SPI at 25 MHz

High speed synchronization capability

1 GHz full power analog bandwidth

Integrated input buffer

On-chip reference, no external decoupling required

Low power dissipation

695 mW at 500 MSPS

Programmable input voltage range

1.18 V to 1.6 V, 1.5 V nominal

1.9 V analog and digital supply operation

1.9 V or 3.3 V SPI and SPORT operation

Clock duty cycle stabilizer

Integrated data clock output with programmable clock and

data alignment

APPLICATIONS

Wireless and wired broadband communications

Communications test equipment

Power amplifier linearization