AD6634BBC屬于RF/IF射頻/中頻RFID的射頻混頻器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6634BBC射頻混頻器射頻混頻器又稱(chēng)混頻器，這些器件具有三個(gè)端口，用于改變兩個(gè)輸入信號(hào)的頻率。射頻混頻器是一些無(wú)源或有源器件，可用于對(duì)信號(hào)進(jìn)行上下變頻。特征包括射頻類(lèi)型、頻率、混頻器數(shù)、增益、噪聲系數(shù)、輔助屬性、電流和電壓。頻率范圍為 0 至 90 GHz，混頻器數(shù)為 1、2、3 或 4。

GENERAL DESCRIPTION

The AD6634 is a multimode 4-channel digital receive signal processor (RSP) capable of processing up to two WCDMA channels. Each channel consists of four cascaded signal processing elements: a frequency translator, two fixed coefficient decimating filters, and a programmable coefficient decimating filter. Each input port has input level threshold detection circuitry and an AGC controller for accommodating large dynamic ranges or situations where gain ranging converters are used. Dual 16-bit parallel output ports accommodate high data rate WBCDMA applications. On-chip interpolating half-band can also be used to further increase the output rate. In addition, each parallel output port has a digital AGC for output data scaling. Link port outputs are provided to enable glueless interfaces to ADI’s TigerSHARC? DSP core.

FEATURES

80 MSPS Wideband Inputs (14 Linear Bits Plus Three

RSSI)

Processes Two WCDMA Channels (UMTS or CDMA2000

1x) or Four GSM/EDGE, IS136 Channels

Four Independent Digital Receivers in a Single Package

Dual 16-Bit Parallel Output Ports

Dual 8-Bit Link Ports

Programmable Digital AGC Loops with 96 dB Range

Digital Resampling for Noninteger Decimation Rates

Programmable Decimating FIR Filters

Interpolating Half-Band Filters

Programmable Attenuator Control for Clip Prevention

and External Gain Ranging via Level Indicator

Flexible Control for Multicarrier and Phased Array

3.3 V I/O, 2.5 V CMOS Core

User Configurable Built-In Self-Test (BIST) Capability

JTAG Boundary Scan

APPLICATIONS

Multicarrier, Multimode Digital Receivers

GSM, IS136, EDGE, PHS, IS95, UMTS, CDMA2000

Micro and Pico Cell Systems, Software Radios

Wireless Local Loop

Smart Antenna Systems

In Building Wireless Telephony