AD6620AS屬于集成電路（IC）的專用。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6620AS專用該系列產(chǎn)品可提供所需的功能，用以將信息源/信宿連到各種復(fù)雜或范圍狹窄應(yīng)用中的傳感器、變送器、致動器、傳輸介質(zhì)或其他此類端點。例如，汽車安全氣囊驅(qū)動器、車身控制和信息娛樂總線、自適應(yīng)電纜均衡器、智能卡等等。

GENERAL DESCRIPTION

The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible.

FEATURES

High Input Sample Rate

67 MSPS Single Channel Real

33.5 MSPS Diversity Channel Real

33.5 MSPS Single Channel Complex

NCO Frequency Translation

Worst Spur Better than –100 dBc

Tuning Resolution Better than 0.02 Hz

2nd Order Cascaded Integrator Comb FIR Filter

Linear Phase, Fixed Coefficients

Programmable Decimation Rates: 2, 3 . . . 16

5th Order Cascaded Integrator Comb FIR Filter

Linear Phase, Fixed Coefficients

Programmable Decimation Rates: 1, 2, 3 . . . 32

Programmable Decimating RAM Coefficient FIR Filter

Up to 134 Million Taps per Second

256 20-Bit Programmable Coefficients

Programmable Decimation Rates: 1, 2, 3 . . . 32

Bidirectional Synchronization Circuitry

Phase Aligns NCOs

Synchronizes Data Output Clocks

Serial or Parallel Baseband Outputs

Pin Selectable Serial or Parallel

Serial Works with SHARC?, ADSP-21xx, Most Other DSPs

16-Bit Parallel Port, Interleaved I and Q Outputs

Two Separate Control and Configuration Ports

Generic μP Port, Serial Port

3.3 V Optimized CMOS Process

JTAG Boundary Scan