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AD1974

4 ADC with PLL, 192 kHz, 24-Bit Codec

GENERALDESCRIPTION TheAD1974isahighperformance,single-chipADCthatprovidesfouranalog-to-digitalconverters(ADCs)withdifferentialinputsusingtheAnalogDevices,Inc.patentedmultibitsigma-delta(Σ-Δ)architecture.AnSPIportisincluded,allowingamicrocontrollertoenablemute

AD1974

四路ADC，內(nèi)置PLL，192 kHz，24位編解碼器

AD1974是一款高性能的單芯片編解碼器，采用ADI公司專利的多比特Σ-Δ架構(gòu)，可提供4個(gè)帶差分輸入的模數(shù)轉(zhuǎn)換器（ADC）。內(nèi)置的SPI 端口使微控制器可以調(diào)整音量和許多其它參數(shù)。AD1974采用3.3 V數(shù)字與模擬電源供電，48引腳（單端輸出）LQFP封裝。\n\n AD1974在系統(tǒng)和電路架構(gòu)上都針對(duì)低電磁干擾（EMI）而設(shè)計(jì)。AD1974利用內(nèi)置PLL驅(qū)動(dòng)LR時(shí)鐘或外部晶振的主時(shí)鐘，從而無需單獨(dú)的高頻主時(shí)鐘，而且可與抑制位時(shí)鐘配合使用。ADC采用ADI公司最新的連續(xù)時(shí)間架構(gòu)進(jìn)行設(shè)計(jì)，進(jìn)一步減小了電磁干擾。AD1974采用3.3 V電源供電，實(shí)現(xiàn)了較低功耗，進(jìn)一步降低了電磁輻射。; ? PLL生成或直接主時(shí)鐘\n\n? 低EMI設(shè)計(jì)\n\n? 動(dòng)態(tài)范圍與SNR：107 dB \n\n? THD + N ：?94 dB\n\n? 單電源電壓：3.3 V \n\n? 5 V邏輯輸入容限;

AD1974

4 ADC with PLL

AD1974YSTZ

4 ADC with PLL, 192 kHz, 24-Bit Codec

GENERALDESCRIPTION TheAD1974isahighperformance,single-chipADCthatprovidesfouranalog-to-digitalconverters(ADCs)withdifferentialinputsusingtheAnalogDevices,Inc.patentedmultibitsigma-delta(Σ-Δ)architecture.AnSPIportisincluded,allowingamicrocontrollertoenablemute

AD1974YSTZ-RL

4 ADC with PLL, 192 kHz, 24-Bit Codec

GENERALDESCRIPTION TheAD1974isahighperformance,single-chipADCthatprovidesfouranalog-to-digitalconverters(ADCs)withdifferentialinputsusingtheAnalogDevices,Inc.patentedmultibitsigma-delta(Σ-Δ)architecture.AnSPIportisincluded,allowingamicrocontrollertoenablemute

AD1974_13

4 ADC with PLL

AD1974WBSTZ

4 ADC with PLL

AD1974WBSTZ-RL

4 ADC with PLL

AD1974YSTZ

4 ADC with PLL

AD1974YSTZ-RL

4 ADC with PLL