描述 Description

The 9ZML1232E/9ZML1252E are a second generation

2-input/12-output differential mux for Intel Purley and newer

platforms. It exceeds the demanding DB1200ZL performance

specifications and is backwards compatible to the 9ZML1232B. It

utilizes Low-Power HCSL-compatible outputs to reduce power

consumption and termination resistors. It is suitable for

PCI-Express Gen1–4 or QPI/UPI applications, and provides 2

configurable low-drift I2O settings, one for each input channel, to

allow I2O tuning for various topologies.

PCIe Clocking Architectures

? Common Clocked (CC)

? Separate Reference No Spread (SRNS)

? Separate Reference Independent Spread (SRIS)

Typical Applications

Servers, Storage, Networking, SSDs

Output Features

? 12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E)

? 12 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout

(9ZML1252E)

特性 Features

? 2 configurable low drift I2O delays up to 2.9ns; maintain

transport delay for various topologies

? LP-HCSL outputs; eliminate 24 resistors (9ZML1232E)

? LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors

(9ZML1252E)

? 9 selectable SMBus addresses; multiple devices can share

same SMBus segment

? Separate VDDIO for outputs; allows maximum power savings

? PLL or Bypass Mode; PLL can dejitter incoming clock

? Hardware or software-selectable PLL BW; minimizes jitter

peaking in downstream PLLs

? Spread spectrum compatible; tracks spreading input clock for

EMI reduction

? SMBus interface; software can modify device settings without

hardware changes

? 10 × 10 mm 72-VFQFPN package; small board footprint

Key Specifications

? Cycle-to-cycle jitter < 50ps

? Output-to-output skew < 50ps

? Input-to-output delay: Fixed at 0 ps

? Input-to-output delay variation < 50ps

? Phase jitter: PCIe Gen4 < 0.5ps rms

? Phase jitter: UPI > 9.6GB/s < 0.1ps rms