74VHCT373AT屬于集成電路（IC）的鎖存器。由意法半導體集團制造生產(chǎn)的74VHCT373AT鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號有效時反映輸入的當前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

DESCRIPTION

The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN.), VIL = 0.8V (MAX)

■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 4.5V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: VOLP = 0.9V (MAX.)