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74VHC595PW

8-bit serial-in/serial-out or parallel-out shift register with output latches

1.Generaldescription The74VHC595;74VHCT595arehigh-speedSi-gateCMOSdevicesandarepincompatiblewith Low-powerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardNo.7A. The74VHC595;74VHCT595are8-stageserialshiftregisterswithastorageregisterand3-state

74VHC595PW

8-bit serial-in/serial-out or parallel-out shift register with output latches

Generaldescription The74VHC595;74VHCT595arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithLow-powerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardNo.7A. The74VHC595;74VHCT595are8-stageserialshiftregisterswithastorageregisterand3-stateout

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74VHC595PW

8-bit serial-in_serial-out or parallel-out shift register; ? Balanced propagation delays\n? All inputs have Schmitt-trigger action\n? Inputs accept voltages higher than VCC\n? Input levels:? The 74VHC595 operates with CMOS input level\n? For 74VHCT595 operates with TTL input level\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n? CDM JESD22-C101E exceeds 1000 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The shift registers have separate clocks.\n Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.\n The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.\n

74VHC595PW-Q100

8-bit serial-in/serial-out or parallel-out shift register with output latches

74VHC595PW,118

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 功能：串行至并行，串行 類別：集成電路（IC） 移位寄存器 描述：IC SHIFT REG 8BIT SISO 16TSSOP

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74VHC595PW-Q100J

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 功能：串行至并行，串行 類別：集成電路（IC） 移位寄存器 描述：IC SHIFT REG 8BIT SISO

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