74VHC174屬于集成電路（IC）的觸發(fā)器。由意法半導體集團制造生產(chǎn)的74VHC174觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復位）和 JK，對提供給其輸入的信號有不同的響應，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。

DESCRIPTION

The 74VHC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.

When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

fMAX = 175MHz (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ HIGH NOISE IMMUNITY:

VNIH = VNIL = 28 VCC (MIN.)

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: VOLP = 0.8V (MAX.)