74V1T77屬于集成電路（IC）的鎖存器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74V1T77鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

DESCRIPTION

The 74V1T77 is an advanced high-speed CMOS SINGLE D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is designed to operate from 4.5V to 5.5V, making this device ideal for portable applications.

The single D-Type latch is controlled by an Latch Enable Input (LE). While the LE input is held at a high level, the Q output will follow the data input precisely. When the LE input is taken low the Q output is latched precisely at the logic level of D data input.

Power down protection is provided on inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

It’s available in the commercial and extended temperature range.

All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4.7ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION: ICC = 1μA(MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX)

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V

■ IMPROVED LATCH-UP IMMUNITY