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74LVCH162373A集成電路(IC)的鎖存器規(guī)格書PDF中文資料

74LVCH162373A
廠商型號(hào)

74LVCH162373A

參數(shù)屬性

74LVCH162373A 封裝/外殼為48-TFSOP(0.240",6.10mm 寬);包裝為管件;類別為集成電路(IC)的鎖存器;產(chǎn)品描述:IC 16BIT D TRANSP LATCH 48TSSOP

功能描述

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

封裝外殼

48-TFSOP(0.240",6.10mm 寬)

文件大小

246.02 Kbytes

頁面數(shù)量

14

生產(chǎn)廠商

NEXPERIA Nexperia B.V. All rights reserved

中文名稱

安世 安世半導(dǎo)體(中國)有限公司

網(wǎng)址

網(wǎng)址

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下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-17 23:01:00

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74LVCH162373A規(guī)格書詳情

1. General description

The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω

termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with

bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16-

bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables

(1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches.

In this condition the latches are transparent, a latch output will change each time its corresponding

D-input changes. When nLE is LOW the latches store the information that was present at the inputs

a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to

assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the

latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

These devices are fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the devices

when they are powered down.

2. Features and benefits

? Overvoltage tolerant inputs to 5.5 V

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power consumption

? Multibyte flow-through standard pinout architecture

? Multiple low inductance supply pins for minimum noise and ground bounce

? Direct interface with TTL levels

? All data inputs have bus hold (74LVCH162373A only)

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    74LVCH162373ADGG,5

  • 制造商:

    Nexperia USA Inc.

  • 類別:

    集成電路(IC) > 鎖存器

  • 系列:

    74LVCH

  • 包裝:

    管件

  • 邏輯類型:

    D 型透明鎖存器

  • 電路:

    8:8

  • 輸出類型:

    三態(tài)

  • 電壓 - 供電:

    1.2V ~ 3.6V

  • 延遲時(shí)間 - 傳播:

    3.3ns

  • 電流 - 輸出高、低:

    12mA,12mA

  • 工作溫度:

    -40°C ~ 125°C

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    48-TFSOP(0.240",6.10mm 寬)

  • 供應(yīng)商器件封裝:

    48-TSSOP

  • 描述:

    IC 16BIT D TRANSP LATCH 48TSSOP

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
PHI
24+
NA/
1529
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詢價(jià)
RENESAS(瑞薩)/IDT
24+
7350
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恩XP
1950+
TSSOP48
4856
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詢價(jià)
恩XP
2023+
SSOP
4446
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詢價(jià)
NEXPERIA/安世
1446
2063
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詢價(jià)
恩XP
25+
SOP
3200
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詢價(jià)
恩XP
25+
25000
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詢價(jià)
24+
5000
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詢價(jià)
NEXPERIA/安世
25+
SOT362
860000
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詢價(jià)
NEXPERIA/安世
22+
SOT370-1
10990
原裝正品
詢價(jià)