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74LVC821A_1中文資料etc未分類制造商數(shù)據(jù)手冊PDF規(guī)格書

廠商型號 |
74LVC821A_1 |
功能描述 | 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state |
文件大小 |
123.19 Kbytes |
頁面數(shù)量 |
20 頁 |
生產(chǎn)廠商 | List of Unclassifed Manufacturers |
企業(yè)簡稱 |
ETC2【etc未分類制造商】 |
中文名稱 | etc2未分類制造商 |
原廠標識 | |
數(shù)據(jù)手冊 | |
更新時間 | 2025-8-1 17:17:00 |
人工找貨 | 74LVC821A_1價格和庫存,歡迎聯(lián)系客服免費人工找貨 |
74LVC821A_1規(guī)格書詳情
General description
The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
特性 Features
■ 5 V tolerant inputs and outputs; for interfacing with 5 V logic
■ Wide supply voltage range from 1.2 V to 3.6 V
■ Inputs accept voltages up to 5.5 V
■ CMOS low power consumption
■ Direct interface with TTL levels
■ Flow-through pin-out architecture
■ 10-bit positive edge-triggered register
■ Independent register and 3-state buffer operation
■ Complies with JEDEC standard JESD8-B
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Specified from ?40 °C to +85 °C and ?40 °C to +125 °C.
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
PHI |
2018+ |
SOP |
6528 |
承若只做進口原裝正品假一賠十! |
詢價 | ||
PHI |
25+ |
NA |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價 | ||
PHI |
SOP24 |
68500 |
一級代理 原裝正品假一罰十價格優(yōu)勢長期供貨 |
詢價 | |||
恩XP |
24+ |
1000 |
詢價 | ||||
PHI |
23+ |
SOP |
12300 |
詢價 | |||
PHI |
22+ |
SOP |
39412 |
原裝正品現(xiàn)貨 |
詢價 | ||
ph |
24+ |
N/A |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
PHI |
22+ |
SOP |
18000 |
原裝正品 |
詢價 | ||
Nexperia |
2022+ |
原廠原包裝 |
8600 |
全新原裝 支持表配單 中國著名電子元器件獨立分銷 |
詢價 | ||
恩XP |
22+ |
24VFQFN |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價 |