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74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The74LVC74Aisahigh-performance,low-voltageSi-gateCMOSdeviceandsuperiortomostadvancedCMOScompatibleTTLfamilies. FEATURES ?Widesupplyvoltagerangeof1.2Vto3.6V ?InaccordancewithJEDECstandardno.8-1A. ?Inputsacceptvoltagesupto5.5V ?CMOSlowpowerc

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74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

Generaldescription The74LVC74AisadualedgetriggeredD-typeflip-flopwithindividualdata(D)inputs,clock(CP)inputs,set(SD)and(RD)inputs,andcomplementaryQandQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyoftheclockinput.Informati

ETC

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

1.Generaldescription The74LVC74AisadualedgetriggeredD-typeflip-flopwithindividualdata(nD)inputs,clock(nCP) inputs,set(nSD)and(nRD)inputs,andcomplementarynQandnQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyoftheclock input

74LVC74ABQ

Dual D-type flip-flop with set and reset; positive-edge trigger

Generaldescription The74LVC74AisadualedgetriggeredD-typeflip-flopwithindividualdata(D)inputs,clock(CP)inputs,set(SD)and(RD)inputs,andcomplementaryQandQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyoftheclockinput.Informati

ETC

74LVC74ABQ

Dual D-type flip-flop with set and reset; positive-edge trigger

1.Generaldescription The74LVC74AisadualedgetriggeredD-typeflip-flopwithindividualdata(nD)inputs,clock(nCP) inputs,set(nSD)and(nRD)inputs,andcomplementarynQandnQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyoftheclock input

74LVC74ABQ-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

Generaldescription The74LVC74A-Q100isadualedgetriggeredD-typeflip-flop.Ithasindividualdata(nD)inputs,clock(nCP)inputs,set(nSD)and(nRD)inputs,andcomplementarynQandnQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyoftheclockin

74LVC74ABQ-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? 5 V tolerant inputs for interlacing with 5 V logic\n? Wide supply voltage range from 1.2 V to 3.6 V\n? CMOS low power consumption\n? Direct interface with TTL levels\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? Multiple package options\n;

The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.\n Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74LVC74ABZ

D-Type Flip-Flops;

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.\n Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.\n

74LVC74AD

Dual D-type flip-flop with set and reset; positive-edge trigger; ? 5 V tolerant inputs for interlacing with 5 V logic\n? Wide supply voltage range from 1.2 V to 3.6 V\n? CMOS low power consumption\n? Direct interface with TTL levels\n? Complies with JEDEC standard:? JESD8-7A (1.65 V to 1.95 V)\n? JESD8-5A (2.3 V to 2.7 V)\n? JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-B exceeds 200 V\n? CDM JESD22-C101E exceeds 1000 V\n\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C\n;

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.\n Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.\n

74LVC74AD

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The74LVC74Aisahigh-performance,low-voltageSi-gateCMOSdeviceandsuperiortomostadvancedCMOScompatibleTTLfamilies. FEATURES ?Widesupplyvoltagerangeof1.2Vto3.6V ?InaccordancewithJEDECstandardno.8-1A. ?Inputsacceptvoltagesupto5.5V ?CMOSlowpowerc

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