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74LVC3G07DP

Triple buffer with open-drain output

Generaldescription The74LVC3G07isahigh-performance,low-power,low-voltage,Si-gateCMOSdeviceandsuperiortomostadvancedCMOScompatibleTTLfamilies. Inputcanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallowstheuseofthisdeviceinamixed3.3Vand5Venvironme

PHI

74LVC3G07DP

Triple buffer with open-drain output

Generaldescription The74LVC3G07providesthreenon-invertingbuffers.Theoutputofthedeviceisanopen-drainandcanbeconnectedtootheropen-drainoutputstoimplementactive-LOWwired-ORoractive-HIGHwired-ANDfunctions.Inputcanbedrivenfromeither3.3Vor5Vdevices.Thisfeat

恩XP

74LVC3G07DP

絲?。?a target="_blank" title="Marking" href="/v07/marking.html">V07；Package：SOT505-2；Triple buffer with open-drain output

1.Generaldescription The74LVC3G07providesthreenon-invertingbuffers. Theoutputofthedeviceisanopen-drainandcanbeconnectedtootheropen-drainoutputsto implementactive-LOWwired-ORoractive-HIGHwired-ANDfunctions. Inputcanbedrivenfromeither3.3Vor5Vdevices.This

74LVC3G07DP

Triple buffer with open-drain output

The 74LVC3G07 provides three non-inverting buffers.\n The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.\n Input can be driven from either 3.3 V or 5 V devices. This feature allows the ; ? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant input/output for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8-B/JESD36 (2.7 V to 3.6 V).\n\n? ESD protection:? HBM JESD22-A114F exce;

74LVC3G07DP-Q100

Triple buffer with open-drain output

The 74LVC3G07-Q100 provides three non-inverting buffers.\n The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.\n Input can be driven from either 3.3 V or 5 V devices. This feature allows; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant input/output for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:;

74LVC3G07DP-Q100

絲?。?a target="_blank" title="Marking" href="/v07/marking.html">V07；Package：TSSOP8；Triple buffer with open-drain output

74LVC3G07DP,125

Package：8-TSSOP，8-MSOP（0.118"，3.00mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 緩沖器，驅(qū)動器，接收器，收發(fā)器 描述：IC BUF NON-INVERT 5.5V 8TSSOP

74LVC3G07DP-Q100H

Package：8-TSSOP，8-MSOP（0.118"，3.00mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 緩沖器，驅(qū)動器，接收器，收發(fā)器 描述：IC BUF NON-INVERT 5.5V 8TSSOP