74LVC374ADTR2G屬于集成電路（IC）的觸發(fā)器。由安森美半導(dǎo)體公司制造生產(chǎn)的74LVC374ADTR2G觸發(fā)器觸發(fā)器是能夠存儲單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲的數(shù)據(jù)，另一個(gè)用于指示存儲該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號時(shí)才會改變。

Low-Voltage CMOS Octal D-Type Flip-Flop

With 5 V?Tolerant Inputs and Outputs (3?State, Non?Inverting)

The 74LVC374A is a high performance, non?inverting octal D?type flip?flop operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows 74LVC374A inputs to be safely driven from 5 V devices.

The 74LVC374A consists of 8 edge?triggered flip?flops with individual D?type inputs and 3?state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flip?flops. The eight flip?flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW?to?HIGH Clock (CP) transition. With the OE LOW, the contents of the eight flip?flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip?flops.

特性 Features

? Designed for 1.2 to 3.6 V VCC Operation

? 5 V Tolerant ? Interface Capability With 5 V TTL Logic

? Supports Live Insertion and Withdrawal

? IOFF Specification Guarantees High Impedance When VCC = 0 V

? 24 mA Output Sink and Source Capability

? Near Zero Static Supply Current in All Three Logic States (10 A)

Substantially Reduces System Power Requirements

? ESD Performance:

? Human Body Model >2000 V

? Machine Model >200 V

? These are Pb?Free Devices