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74LVC2G04

Dual inverter

1.Generaldescription The74LVC2G04isadualinverter.Inputscanbedrivenfromeither3.3Vor5Vdevices.This featureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinputrisea

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

74LVC2G04

Dual Inverter; ? 1.65V to 5.5V Wide Operating Voltage Range\n\n? Input and Output Interface Capability to 5V System Environment\n\n? +24mA/-24mA Output Current at VCC?= 3.0V\n\n? CMOS Low Power Consumption\n\n? Direct Interface with TTL Levels\n\n? High Noise Immunity\n\n? -40℃?to +125℃?Operating Temperature Range\n\n? Available in Green SOT-23-6 and SC70-6 Packages;

The 74LVC2G04 contains two independent inverters and it is designed for 1.65V to 5.5V VCC?operation. The inputs from 3.3V or 5V devices make this device can be used as a translator in a mixed 3.3V and 5V system environment. The device features the Boolean function Y =?A.\nThis device is suitable for partial power-down applications using IOFF. When the device is powered down, the damaging current backflow will be prevented from passing through the device.\n

SGMICROSG Micro Corp

圣邦股份圣邦微電子（北京）股份有限公司

74LVC2G04

Dual-gate;

The 74LVC2G04 is a dual inverter gate with standard pushpull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Y = A

DiodesDiodes Incorporated

美臺(tái)半導(dǎo)體

74LVC2G04

Dual inverter

PanasonicPanasonic Semiconductor

松下松下電器

74LVC2G04

Dual inverter

ETC

ETC

74LVC2G04

DUAL INVERTER GATE

DIODESDiodes Incorporated

美臺(tái)半導(dǎo)體

74LVC2G04GM

Dual inverter; ? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant inputs for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8B/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? ±24 mA output drive (VCC = 3.0 V)\n? CMOS low power consumption\n? Latch-up performance exceeds 250 mA\n? Direct interface with TTL levels\n? Inputs accept voltages up to 5 V\n? Multiple package options\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C\n;

The 74LVC2G04 provides the dual inverting buffer.\n Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n

NexperiaNexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

74LVC2G04GM

絲?。?a target="_blank" title="Marking" href="/v4/marking.html">V4；Package：SOT886；Dual inverter

1.Generaldescription The74LVC2G04isadualinverter.Inputscanbedrivenfromeither3.3Vor5Vdevices.This featureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinputrisea

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

74LVC2G04GN

絲?。?a target="_blank" title="Marking" href="/v4/marking.html">V4；Package：SOT1115；Dual inverter

1.Generaldescription The74LVC2G04isadualinverter.Inputscanbedrivenfromeither3.3Vor5Vdevices.This featureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinputrisea

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

74LVC2G04GS

絲印：V4；Package：SOT1202；Dual inverter

1.Generaldescription The74LVC2G04isadualinverter.Inputscanbedrivenfromeither3.3Vor5Vdevices.This featureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinputrisea

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

技術(shù)參數(shù)

  • Number of Gates：

    2

  • Family：

    LVC

  • VCC Min：

    1.65 V

  • VCC Max：

    5.5 V

  • tpd max @ (1.5V)：

    - ns

  • tpd max @ (1.8V)：

    8 ns

  • tpd max @ (2.5V)：

    4.4 ns

  • tpd max @ (3.3V)：

    4.1 ns

  • tpd max @ (5.0V)：

    3.2 ns

  • Input/ Output Current：

    32

  • Output Type：

    Push-Pull

  • Packages：

    SOT26 (SC74R)/SOT363/X2-DFN1010-6/X2-DFN1409-6/X2-DFN1410-6

供應(yīng)商型號(hào)品牌批號(hào)封裝庫(kù)存備注價(jià)格
SMD
23+
NA
15659
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24+
SOT-363
15
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ANALOG
5000
PH3
35000
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2016+
XSON
30000
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QFN
3000
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12+
TO-263
15000
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恩XP
23+
XSON6QFN
5000
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恩XP
16+
SOT23-6
3000
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PHI
24+
XSON6QFN
25843
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恩XP
2020+
TSOP6
50
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更多74LVC2G04供應(yīng)商 更新時(shí)間2025-7-30 17:55:00

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