描述 Description

The 74LVC240A is a high performance, inverting octal buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows 74LVC240A inputs to be safely driven from 5 V devices. The 74LVC240A is suitable for memory address driving and all TTL level bus oriented transceiver applications.Current drive capability is 24mA at the outputs. The Output Enable(OEbar) input, when HIGH, disables the outputs by placing them in a HIGH Z condition.

特性 Features

Designed for 1.2 V to 3.6 V VCC Operation
5 V Tolerant ? Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 μA) Substantially Reduces System Power Requirements
Latchup Performance Exceeds 250 mA
ESD Performance: Human Body Model >2000 V; Machine Model >200 V
These Devices are Pb?Free, Halogen Free/BFR Free and are RoHS Compliant

簡(jiǎn)介

74LVC240屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由制造生產(chǎn)的74LVC240緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪(fǎng)問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線(xiàn)之間進(jìn)行隔離通信。