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首頁>74LVC1G14GZ-Q100>規(guī)格書詳情

74LVC1G14GZ-Q100中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書

74LVC1G14GZ-Q100
廠商型號(hào)

74LVC1G14GZ-Q100

功能描述

Single Schmitt trigger inverter

絲印標(biāo)識(shí)

VF

封裝外殼

XSON5

文件大小

280.68 Kbytes

頁面數(shù)量

17

生產(chǎn)廠商

NEXPERIA Nexperia B.V. All rights reserved

中文名稱

安世 安世半導(dǎo)體(中國)有限公司

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-15 18:35:00

人工找貨

74LVC1G14GZ-Q100價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

74LVC1G14GZ-Q100規(guī)格書詳情

1. General description

The 74LVC1G14-Q100 is a single inverter with Schmitt-trigger inputs. Inputs can be driven from

either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed

3.3 V and 5 V environments. This device is fully specified for partial power down applications using

IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current

through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? CMOS low power dissipation

? IOFF circuitry provides partial Power-down mode operation

? ±24 mA output drive (VCC = 3.0 V)

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? Unlimited rise and fall times

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? JESD36 (4.5 V to 5.5 V)

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

? Multiple package options

3. Applications

? Wave and pulse shaper

? Astable multivibrator

? Monostable multivibrator

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