74LVC1G07GW-Q100屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74LVC1G07GW-Q100緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

1. General description

The 74LVC1G07-Q100 is a single buffer with open-drain output. Inputs can be driven from either

3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V

and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input

rise and fall times. This device is fully specified for partial power down applications using IOFF. The

IOFF circuitry disables the output, preventing the potentially damaging backflow current through the

device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? CMOS low power consumption

? IOFF circuitry provides partial Power-down mode operation

? -24 mA output drive (VCC = 3.0 V)

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? JESD36 (4.5 V to 5.5 V)

? ESD protection:

? MIL-STD-883, method 3015 exceeds 2000 V

? HBM, ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V

? MM, JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

? Multiple package options