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74LVC1G04GX

Marking：VC；Package：SOT1226-3；Single inverter

1.Generaldescription The74LVC1G04isasingleinverter.Inputscanbedrivenfromeither3.3Vor5Vdevices.This featureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinputrise

74LVC1G04GX

Single inverter; ? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant inputs for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8-B/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V\n? MM: JESD22-A115-A exceeds 200 V\n\n? ±24 mA output drive (VCC = 3.0 V)\n? CMOS low power consumption\n? Latch-up performance exceeds 250 mA\n? Direct interface with TTL levels\n? Inputs accept voltages up to 5 V\n? Multiple package options\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C.\n;

The 74LVC1G04 provides one inverting buffer.\n Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n

74LVC1G04GX4

Single inverter; ? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant inputs for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8-B/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V\n? MM: JESD22-A115-A exceeds 200 V\n\n? ±24 mA output drive (VCC = 3.0 V)\n? CMOS low power consumption\n? Latch-up performance exceeds 250 mA\n? Direct interface with TTL levels\n? Inputs accept voltages up to 5 V\n? Multiple package options\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C.\n;

The 74LVC1G04 provides one inverting buffer.\n Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n

74LVC1G04GX4

Marking：VC；Package：SOT1269-2；Single inverter

1.Generaldescription The74LVC1G04isasingleinverter.Inputscanbedrivenfromeither3.3Vor5Vdevices.This featureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinputrise

74LVC1G04GX,125

Package：4-XFDFN 裸露焊盤；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 門和反相器 描述：IC INVERTER 1CH 1-INP 5X2SON

Nexperia USA Inc.

74LVC1G04GX4Z

Package：4-XFDFN；包裝：卷帶（TR） 類別：集成電路（IC） 門和反相器 描述：IC INVERTER 1CH 1-INP 4X2SON

Nexperia USA Inc.