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74LVC00APW

Quad 2-input NAND gate

DESCRIPTION The74LVC00Aisahigh-performance,lowpower,low-voltage,Si-gateCMOSdeviceandsuperiortomostadvancedCMOScompatibleTTLfamilies. FEATURES ?Widesupplyrangeof1.2Vto3.6V ?ComplieswithJEDECstandardno.8-1A ?Inputsacceptvoltagesupto5.5V ?CMOSlowpow

74LVC00APW

Quad 2-input NAND gate

1.Generaldescription The74LVC00Aisaquad2-inputNANDgate.Inputscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5Venvironments. Schmitt-triggeractionatallinputsmakesthecircuittolerantofslowerinpu

74LVC00APW

Quad 2-input NAND gate; ? 5 V tolerant inputs for interfacing with 5 V logic\n? Wide supply voltage range from 1.2 V to 3.6 V\n? CMOS low power consumption\n? Direct interface with TTL levels\n? Complies with JEDEC standard:? JESD8-7A (1.65 V to 1.95 V)\n? JESD8-5A (2.3 V to 2.7 V)\n? JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-B exceeds 200 V\n? CDM JESD22-C101E exceeds 1000 V\n\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C\n;

The 74LVC00A provides four 2-input NAND gates.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.\n

74LVC00APW

Quad 2-input NAND gate Rev. 7 ??25 April 2012

74LVC00APWDH

Quad 2-input NAND gate

DESCRIPTION The74LVC00Aisahigh-performance,lowpower,low-voltage,Si-gateCMOSdeviceandsuperiortomostadvancedCMOScompatibleTTLfamilies. FEATURES ?Widesupplyrangeof1.2Vto3.6V ?ComplieswithJEDECstandardno.8-1A ?Inputsacceptvoltagesupto5.5V ?CMOSlowpow

74LVC00APW-Q100

Quad 2-input NAND gate; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? 5 V tolerant inputs for interfacing with 5 V logic\n? Wide supply voltage range from 1.2 V to 3.6 V\n? CMOS low power consumption\n? Direct interface with TTL levels\n? Complies with JEDEC standard:? JESD8-7A (1.65 V to 1.95 V)\n? JESD8-5A (2.3 V to 2.7 V)\n? JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? Multiple package options\n;

The 74LVC00A-Q100 provides four 2-input NAND gates.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74LVC00APW-118

Quad 2-input NAND gate Rev. 7 ??25 April 2012

74LVC00APW-Q100

Quad 2-input NAND gate

74LVC00APW,112

Package：14-TSSOP（0.173"，4.40mm 寬）；包裝：管件 類別：集成電路（IC） 門和反相器 描述：IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

74LVC00APW,118

Package：14-TSSOP（0.173"，4.40mm 寬）；包裝：管件 類別：集成電路（IC） 門和反相器 描述：IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.