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74HCT374D

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERALDESCRIPTION The74HC/HCT374arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL (LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?3-statenon-invertingoutputsforbusorientedapplications ?8-bitpositive,

74HCT374D

Octal D-type flip-flop; positive edge-trigger; 3-state

1.Generaldescription The74HC374;74HCT374isanoctalpositive-edgetriggeredD-typeflip-flopwith3-stateoutputs. Thedevicefeaturesaclock(CP)andoutputenable(OE)inputs.Theflip-flopswillstorethestate oftheirindividualD-inputsthatmeettheset-upandholdtimerequirement

74HCT374D

Octal D-type flip-flop; positive-edge trigger; 3-state; ? Input levels:? For 74HC374: CMOS level\n? For 74HCT374: TTL level\n\n? Octal bus interface\n? Non-inverting 3-state outputs\n? 8-bit positive, edge-triggered register\n? Common 3-state output enable input\n? Independent register and 3-state buffer operation\n? Complies with JEDEC standard no. 7 A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C\n;

The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3?state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip?flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip?-?flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n The 74HCT374 features reduced input threshold levels to allow interfacing to TTL logic levels.\n

74HCT374DB

Octal D-type flip-flop; positive-edge trigger; 3-state; ? Input levels:? For 74HC374: CMOS level\n? For 74HCT374: TTL level\n\n? Octal bus interface\n? Non-inverting 3-state outputs\n? 8-bit positive, edge-triggered register\n? Common 3-state output enable input\n? Independent register and 3-state buffer operation\n? Complies with JEDEC standard no. 7 A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C\n;

The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3?state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip?flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip?-?flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n The 74HCT374 features reduced input threshold levels to allow interfacing to TTL logic levels.\n

74HCT374DB

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERALDESCRIPTION The74HC/HCT374arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL (LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?3-statenon-invertingoutputsforbusorientedapplications ?8-bitpositive,

74HCT374D,653

Package：20-SOIC（0.295"，7.50mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：標準 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 8BIT 20SO

Nexperia USA Inc.

74HCT374DB,112

Package：20-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：標準 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

Nexperia USA Inc.

74HCT374DB,118

Package：20-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：標準 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

Nexperia USA Inc.