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74HCT273BQ

Octal D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC273;74HCT273isanoctalpositive-edgetriggeredD-typeflip-flop.Thedevice featuresclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethestateoftheir correspondingDninputsthatmeettheset-upandholdtimerequirementsontheLOW-to-HIG

74HCT273BQ

Octal D-type flip-flop with reset; positive-edge trigger; ? Input levels:? For 74HC273: CMOS level\n? For 74HCT273: TTL level\n\n? Common clock and master reset\n? Eight positive edge-triggered D-type flip-flops\n? Complies with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HCT273BQ-Q100

Octal D-type flip-flop with reset; positive-edge trigger; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40°C to +85°C and from -40°C to +125°C\n\n? Input levels:? For 74HC273-Q100: CMOS level\n? For 74HCT273-Q100: TTL level\n\n? Common clock and master reset\n? Eight positive edge-triggered D-type flip-flops\n? Complies with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000V\n? MM JESD22-A115-A exceeds 200V\n\n? Multiple package options\n;

The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D?type flip?flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW?to?HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HCT273BQ-Q100

Octal D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC273-Q100;74HCT273-Q100isanoctalpositive-edgetriggeredD-typeflip-flop.The devicefeaturesclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethe stateoftheircorrespondingDninputsthatmeettheset-upandholdtimerequirementsonthe

74HCT273BQ-Q100

Octal D-type flip-flop with reset; positive-edge trigger

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74HCT273BQ,115

Package：20-VFQFN 裸露焊盤(pán)；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：主復(fù)位 類(lèi)別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN

ETC

74HCT273BQ-Q100X

Package：20-VFQFN 裸露焊盤(pán)；包裝：卷帶（TR） 功能：主復(fù)位 類(lèi)別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN

ETC