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74HCT163PW數(shù)據(jù)手冊(cè)集成電路(IC)的計(jì)數(shù)器除法器規(guī)格書(shū)PDF

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廠商型號(hào)

74HCT163PW

參數(shù)屬性

74HCT163PW 封裝/外殼為16-TSSOP(0.173",4.40mm 寬);包裝為管件;類(lèi)別為集成電路(IC)的計(jì)數(shù)器除法器;產(chǎn)品描述:IC SYNC 4BIT BINRY COUNT 16TSSOP

功能描述

Presettable synchronous 4-bit binary counter; synchronous reset

封裝外殼

16-TSSOP(0.173",4.40mm 寬)

制造商

Nexperia Nexperia B.V. All rights reserved

中文名稱(chēng)

安世 安世半導(dǎo)體(中國(guó))有限公司

數(shù)據(jù)手冊(cè)

下載地址下載地址二

更新時(shí)間

2025-8-14 23:01:00

人工找貨

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74HCT163PW規(guī)格書(shū)詳情

描述 Description

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula:
fmax= / (tP (max)(CP to TC) + tSU(CEP to CP) )

特性 Features

? Complies with JEDEC standard no. 7A
? Input levels:
? For 74HC163: CMOS level
? For 74HCT163: TTL level

? Synchronous counting and loading
? 2 count enable inputs for n-bit cascading
? Synchronous reset
? Positive-edge triggered clock
? ESD protection:
? HBM JESD22-A114F exceeds 2000 V
? MM JESD22-A115-A exceeds 200 V

? Multiple package options
? Specified from ?40 °C to +85 °C and ?40 °C to +125 °C

應(yīng)用 Application

? Television sets
? Home-sound sets
? Multimedia systems
? All mains fed audio systems
? Car audio (boosters)

技術(shù)參數(shù)

  • 制造商編號(hào)

    :74HCT163PW

  • 生產(chǎn)廠家

    :Nexperia

  • Product status

    :Production

  • V_CC (V)

    :4.5 - 5.5

  • Output drive capability (mA)

    :+/- 4.0

  • Logic switching levels

    :TTL

  • t_pd (ns)

    :20

  • Power dissipation considerations

    :low

  • T_amb (Cel)

    :-40~125

  • R_th(j-a) (K/W)

    :116

  • Ψ_th(j-top) (K/W)

    :2.5

  • R_th(j-c) (K/W)

    :44.7

  • Package name

    :TSSOP16

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24+
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5154
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Nexperia(安世)
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TSSOP16
7350
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26976
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Nexperia
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SO-14
10000
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PHI
25+
TSSOP14
1685
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23+
TSSOP
12300
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04+
SSOP
2104
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SOP
43
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