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74HCT109PW

Dual JK flip-flop with set and reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT109arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT109aredualpositive-edgetriggered,JKflip-flopswithindividualJ,Kinputs,clock(CP)

74HCT109PW

Dual JK flip-flop with set and reset; positive-edge-trigger

1.Generaldescription The74HC109;74HCT109isadualpositiveedgetriggeredJKflip-flopfeaturingindividualJand Kinputs,clock(CP)inputs,set(SD)andreset(RD)inputsandcomplementaryQandQoutputs. ThesetandresetareasynchronousactiveLOWinputsandoperateindependentlyof

74HCT109PW

Dual JK flip-flop with set and reset; positive-edge-trigger; ? Input levels:? For 74HC109: CMOS level\n? For 74HCT109: TTL level\n\n? J and K inputs for easy D-type flip-flop\n? Toggle flip-flop or \"do nothing\" mode\n? Specified in compliance with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip?-?flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip?-?flops as described in the mode select function table. The nJ and nK inputs must be stable one set?-?up time prior to the LOW?-?to?-?HIGH clock transition for predictable operation. The JK design allows operation as a D?-?type flip?-?flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.\n

74HCT109PW-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Input levels:? For 74HC109-Q100: CMOS level\n? For 74HCT109-Q100: TTL level\n\n? J and K inputs for easy D-type flip-flop\n? Toggle flip-flop or \"do nothing\" mode\n? Specified in compliance with JEDEC standard no. 7A\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n;

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip?-?flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip?-?flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HCT109PW-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

1.Generaldescription The74HC109-Q100;74HCT109-Q100isadualpositiveedgetriggeredJKflip-flopfeaturing individualnJandnKinputs.Ithasclock(nCP)inputs,set(nSD)andreset(nRD)inputsand complementarynQandnQoutputs.ThesetandresetareasynchronousactiveLOWinputsand

74HCT109PW,112

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16TSSOP

Nexperia USA Inc.

74HCT109PW,118

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16TSSOP

Nexperia USA Inc.

74HCT109PW-Q100J

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16TSSOP

Nexperia USA Inc.