首頁>74HCT107PW>規(guī)格書詳情
74HCT107PW中文資料飛利浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書
| 廠商型號 |
74HCT107PW |
| 功能描述 | Dual JK flip-flop with reset; negative-edge trigger |
| 文件大小 |
53.67 Kbytes |
| 頁面數(shù)量 |
7 頁 |
| 生產(chǎn)廠商 | PHI |
| 中文名稱 | 飛利浦 |
| 數(shù)據(jù)手冊 | |
| 更新時(shí)間 | 2025-8-15 14:38:00 |
| 人工找貨 | 74HCT107PW價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
相關(guān)芯片規(guī)格書
更多74HCT107PW規(guī)格書詳情
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
FEATURES
? Output capability: standard
? ICC category: flip-flops
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
恩XP |
22+ |
16SOIC |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
恩XP |
24+ |
N/A |
16000 |
原裝正品現(xiàn)貨支持實(shí)單 |
詢價(jià) | ||
PHI |
1725+ |
SOP16 |
6528 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
詢價(jià) | ||
HAR |
24+ |
SOP |
222 |
詢價(jià) | |||
PHIL |
21+ |
SOP |
1989 |
原裝現(xiàn)貨假一賠十 |
詢價(jià) | ||
HAR |
25+ |
SOP |
3200 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售 |
詢價(jià) | ||
恩XP |
24+ |
N/A |
6000 |
原裝，正品 |
詢價(jià) | ||
PHI |
24+ |
SOP |
2987 |
只售原裝自家現(xiàn)貨!誠信經(jīng)營!歡迎來電! |
詢價(jià) | ||
ph |
24+ |
N/A |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價(jià) | ||
恩XP |
24+ |
N/A |
6000 |
現(xiàn)貨 |
詢價(jià) |
