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74HC595DB

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The74HC/HCT595arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT595isan8-stageserialshiftregisterwithastorageregisterand3-stateoutputs.Theshiftregi

74HC595DB

8-bit serial-in, serial or parallel-out shift register with output latches; 3?-?state; ? 8-bit serial input\n? 8-bit serial or parallel output\n? Storage register with 3-state outputs\n? Shift register with direct clear\n? 100 MHz (typical) shift out frequency\n? Complies with JEDEC standard no. 7A\n? Input levels:? For 74HC595: CMOS level\n? For 74HCT595: TTL level\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC595DB-Q100

8-bit serial-in, serial or parallel-out shift register with output latches; 3?-?state; ·Automotive product qualification in accordance with AEC-Q100 (Grade 1)·Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state - The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC595-Q100; 74HCT595-Q100 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74HC595DB-Q100

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

74HC595DB,112

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：串行至并行，串行 類別：集成電路（IC） 移位寄存器 描述：IC 8BIT SHIFT REGISTER 16-SSOP

Nexperia USA Inc.

74HC595DB,118

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：串行至并行，串行 類別：集成電路（IC） 移位寄存器 描述：IC 8BIT SHIFT REGISTER 16SSOP

Nexperia USA Inc.

74HC595DB-Q100J

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 功能：串行至并行，串行 類別：集成電路（IC） 移位寄存器 描述：IC COUNTER REGISTER 8BIT 16SSOP

Nexperia USA Inc.