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74HC573D

Octal D-type transparent latch; 3-state

GENERALDESCRIPTION The74HC/HCT573arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Inputsandoutputsonopposite sidesofpackageallowingeasy interfacewithmicrop

PHI

74HC573D

絲?。?strong>74HC573D；Package：SOIC20；CMOS Digital Integrated Circuits Silicon Monolithic

FunctionalDescription ?OctalD-TypeLatchwith3-StateOutputs General The74HC573DisahighspeedCMOSOCTALLATCHwith3-STATEOUTPUTfabricatedwithsilicongate C2MOStechnology. ItachievesthehighspeedoperationsimilartoequivalentLSTTLwhilemaintainingtheCMOSlowpower diss

74HC573D

Octal D-type transparent latch; 3-state

1.Generaldescription The74HC573;74HCT573isan8-bitD-typetransparentlatchwith3-stateoutputs.Thedevice featureslatchenable(LE)andoutputenable(OE)inputs.WhenLEisHIGH,dataattheinputs enterthelatches.Inthisconditionthelatchesaretransparent,alatchoutputwill

74HC573D

Octal D-type transparent latch; 3-state; ? Input levels:? For 74HC573: CMOS level\n? For 74HCT573: TTL level\n\n? Inputs and outputs on opposite sides of package allowing easy interface with microprocessors\n? Useful as input or output port for microprocessors and microcomputers\n? 3-state non-inverting outputs for bus-oriented applications\n? Common 3-state output enable input\n? Multiple package options\n? Complies with JEDEC standard no. 7 A\n? ESD protection:\n? ? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC573D

74HC CMOS logic IC series; Power Dissipation PD 500 mW \n;

Function：Octal D-Type Latch (3-State)\nNumber of Circuits：8\nRoHS Compatible Product(s) (#)：Available\nAssembly bases：日本\n

74HC573D

Package：20-SOIC（0.295"，7.50mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 鎖存器 描述：IC LATCH OCTAL D 3ST 20SOIC

ETC

74HC573DB

Octal D-type transparent latch; 3-state

GENERALDESCRIPTION The74HC/HCT573arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Inputsandoutputsonopposite sidesofpackageallowingeasy interfacewithmicrop

PHI

74HC573DB-Q100

Octal D-type transparent latch; 3-state; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Input levels:? For 74HC573-Q100: CMOS level\n? For 74HCT573-Q100: TTL level\n\n? Inputs and outputs on opposite sides of package allowing easy interface with microprocessors\n? Useful as input or output port for microprocessors and microcomputers\n? 3-state non-inverting outputs for bus-oriented applications\n? Common 3-state output enable input\n? Multiple package options\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2 000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints\n;

The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HC573D-Q100

Octal D-type transparent latch; 3-state

Generaldescription The74HC573-Q100;74HCT573-Q100isahigh-speedSi-gateCMOSdeviceandispincompatiblewithLow-powerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardno.7A. Featuresandbenefits ■AutomotiveproductqualificationinaccordancewithAEC-Q100(Grad

ETC

74HC573D-Q100

Octal D-type transparent latch; 3-state

1.Generaldescription The74HC573-Q100;74HCT573-Q100isan8-bitD-typetransparentlatchwith3-stateoutputs. Thedevicefeatureslatchenable(LE)andoutputenable(OE)inputs.WhenLEisHIGH,dataat theinputsenterthelatches.Inthisconditionthelatchesaretransparent,alatchou