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74HC4520PW

Dual 4-bit synchronous binary counter

1.Generaldescription The74HC4520;74HCT4520aredual4-bitinternallysynchronousbinarycounterswithtwoclock inputs(nCP0andnCP1).Theyhavebufferedoutputsfromall4bitpositions(nQ0tonQ3)andan asynchronousmasterresetinput(nMR).ThecounteradvancesontheLOW-to-HIGHtran

74HC4520PW

Dual 4-bit synchronous binary counter

GENERALDESCRIPTION The74HC/HCT4520arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“4520”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT4520aredual4-bitinternallysynchronousbinarycounterswithanactiveHIGHclockinp

74HC4520PW

Dual 4-bit synchronous binary counter; ? Complies with JEDEC standard no. 7A\n? Input levels:? For 74HC4520: CMOS level\n? For 74HCT4520: TTL level\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C\n;

The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC4520PW-Q100

Dual 4-bit synchronous binary counter; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Wide supply voltage range from 2.0 V to 6.0 V\n? CMOS low power dissipation\n? High noise immunity\n? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n? Complies with JEDEC standards:? JESD8C (2.7 V to 3.6 V)\n? JESD7A (2.0 V to 6.0 V)\n\n? Input levels:? For 74HC4520-Q100: CMOS level\n? For 74HCT4520-Q100: TTL level\n\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n;

The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either the LOW?-?to?-?HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH?-?to?-?LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HC4520PW-Q100

Dual 4-bit synchronous binary counter

1.Generaldescription The74HC4520-Q100;74HCT4520-Q100aredual4-bitinternallysynchronousbinarycounters withtwoclockinputs(nCP0andnCP1).Theyhavebufferedoutputsfromall4bitpositions (nQ0tonQ3),andanasynchronousmasterresetinput(nMR).Thecounteradvancesoneither t

74HC4520PW,112

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類(lèi)別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC DUAL 4BIT SYNC BINAR 16-TSSOP

Nexperia USA Inc.

74HC4520PW,118

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類(lèi)別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC DUAL 4BIT SYNC BINARY 16TSSOP

Nexperia USA Inc.