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74HC40103DB

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

ETC

74HC40103DB

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

ETC

74HC40103N

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

ETC

74HC40103N

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

74HC40103N

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

ETC

74HC40103PW

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

ETC

74HC40103PW

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

74HC40103PW

8-bit synchronous binary down counter

1.Generaldescription The74HC40103isan8-bitsynchronousdowncounter.Ithascontrolinputsforenabling ordisablingtheclock(CP),forclearingthecountertoitsmaximumcountandfor presettingthecountereithersynchronouslyorasynchronously.Innormaloperation,the counterisde

74HC40103PW

8-bit synchronous binary down counter

GENERALDESCRIPTION The74HC/HCT40103arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“40103”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT40103consisteachofan8-bitsynchronousdowncounterwithasingleoutputwhich

ETC

74HC40103PW

8-bit synchronous binary down counter; ? Cascadable\n? Synchronous or asynchronous preset\n? Low-power dissipation\n? Complies with JEDEC standard no. 7A\n? CMOS input levels\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +80 °C and from -40 °C to +125 °C\n;

The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. Device may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n