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74HC175DB

74HC175DB - Quad D-type flip-flop with reset; positive-edge trigger; ·Input levels:·For 74HC175: CMOS level\n·For 74HCT175: TTL level\n;

Quad D-type flip-flop with reset; positive-edge trigger - The 74HC175; 74HCT175 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.

74HC175DB

Quad D-type flip-flop with reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT175arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT175havefouredge-triggered,D-typeflip-flopswithindividualDinputsandbothQandQo

PHI

74HC175DB,112

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

ETC

74HC175DB,118

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

ETC

74HC175PW

NXP
SSOP

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