74HC174PW-Q100屬于集成電路（IC）的觸發(fā)器。由安世半導體(中國)有限公司制造生產(chǎn)的74HC174PW-Q100觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復位）和 JK，對提供給其輸入的信號有不同的響應，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。

1. General description

The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with

individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR)

inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold

time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at

the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include

clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in

excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 2.0 to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Input levels:

? For 74HC174-Q100: CMOS level

? For 74HCT174-Q100: TTL level

? Six edge-triggered D-type flip-flops

? Asynchronous master reset

? Complies with JEDEC standards

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? ESD protection:

? MIL-STD-883, method 3015 exceeds 2000 V

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)