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74HC125

Quad buffer/line driver; 3-state

GENERALDESCRIPTION The74HC/HCT125arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL). TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Outputcapability:busdriver ?ICCcategory:MSI

74HC125

Quad 3??tate Noninverting Buffers

The74HC125isidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLSTTLoutputs. TheHC125noninvertingbufferisdesignedtobeusedwith3?statememoryaddressdrivers,clockdrivers,andotherbus?orien

74HC125

Quad buffer/line driver; 3-state

1.Generaldescription The74HC125;74HCT125isaquadbuffer/linedriverwith3-stateoutputscontrolledbytheoutput enableinputs(nOE).AHIGHonnOEcausestheoutputstoassumeahighimpedanceOFF-state. Inputsincludeclampdiodes.Thisenablestheuseofcurrentlimitingresistorsto

74HC125

Quad 3??tate Noninverting Buffers

Quad3?StateNoninvertingBuffersHigh?PerformanceSilicon?GateCMOS TheMC74HC125AandMC74HC126AareidenticalinpinouttotheLS125andLS126.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLSTTLoutputs. TheHC125AandHC126An

74HC125

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The74HC125providesprovidesfourindependentbuffergateswith3-stateoutputs.Eachbufferhasaseparateenablepinthatifdrivenwithahighlogiclevelplacesthecorrespondingoutputinthehighimpedancestate.Thedeviceisdesignedforoperationwithapowersupplyrangeof

74HC125

High Speed CMOS Logic

Features OutputDriveCapability:15LSTTLLoads LowInputCurrent:1μA OutputsdirectlyinterfaceCMOS,NMOSandTTL OperatingVoltageRange:2Vto6V Functioncompatiblewith74LS125 HighNoiseImmunityCMOSprocess.

74HC125

QUAD BUS BUFFERS (3-STATE)

DESCRIPTION TheM54/74HC125/126arehighspeedCMOS QUADBUSBUFFER(3-STATE)FABRICATEDIN SILICONGATEC2MOStechnology. Theyhavethesamehighspeedperformanceof LSTTLcombinedwithtrueCMOSlowpowerconsumption. Thesedevicesrequirethesame3-STATEcontrol inputGtobetakenhig

74HC125

Standard-logic;

The 74HC125 provides provides four independent buffer gates with\n3-state outputs. Each buffer has a separate enable pin that if driven\nwith a high logic level places the corresponding output in the high\nimpedance state. The device is designed for operation with a power\nsupply range of 2.0V to 6.0V.

74HC125

QUAD BUS BUFFERS (3-STATE);

74HC125

74系列 邏輯芯片;