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74HC107DB

Dual JK flip-flop with reset; negative-edge trigger; ? Complies with JEDEC standard no. 7A\n? Input levels:? The 74HC107: CMOS levels\n? The 74HCT107: TTL levels\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC107DB

Dual JK flip-flop with reset; negative-edge trigger

GENERALDESCRIPTION The74HC/HCT107arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT107aredualnegative-edgetriggeredJK-typeflip-flopsfeaturingindividualJ,K,cloc

PHI

74HC107DB,112

Package：14-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 14SSOP

ETC

74HC107DB,118

Package：14-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 14SSOP

ETC

74HC112AP

TOSHIBA
DIP-16