描述 Description

The 74AUP3G34 is a triple buffer.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

特性 Features

? Wide supply voltage range from 0.8 V to 3.6 V
? High noise immunity
? Complies with JEDEC standards:
? JESD8-12 (0.8 V to 1.3 V)
? JESD8-11 (0.9 V to 1.65 V)
? JESD8-7 (1.2 V to 1.95 V)
? JESD8-5 (1.8 V to 2.7 V)
? JESD8-B (2.7 V to 3.6 V)

? ESD protection:
? HBM JESD22-A114F Class 3A exceeds 5000 V
? MM JESD22-A115-A exceeds 200 V
? CDM JESD22-C101E exceeds 1000 V

? Low static power consumption; ICC = 0.9 μA (maximum)
? Latch-up performance exceeds 100 mA per JESD 78B Class II
? Inputs accept voltages up to 3.6 V
? Low noise overshoot and undershoot < 10 % of VCC
? IOFF circuitry provides partial Power-down mode operation
? Multiple package options
? Specified from -40 °C to +85 °C and -40 °C to +125 °C

簡(jiǎn)介

74AUP3G34GT屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由制造生產(chǎn)的74AUP3G34GT緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。