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74AUP1G373GW-Q100

Low-power D-type transparent latch; 3-state; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Wide supply voltage range from 0.8 V to 3.6 V\n? High noise immunity\n? Complies with JEDEC standards:? JESD8-12 (0.8 V to 1.3 V)\n? JESD8-11 (0.9 V to 1.65 V)\n? JESD8-7 (1.2 V to 1.95 V)\n? JESD8-5 (1.8 V to 2.7 V)\n? JESD8-B (2.7 V to 3.6 V)\n\n? ESD protection:? MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V\n? HBM JESD22-A114F Class 3A. Exceeds 5000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? Low static power consumption; ICC = 0.9 μA (maximum)\n? Latch-up performance exceeds 100 mA per JESD 78 Class II\n? Inputs accept voltages up to 3.6 V\n? Low noise overshoot and undershoot < 10 % of VCC\n? IOFF circuitry provides partial Power-down mode operation\n;

The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH?-?to?-?LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

NexperiaNexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

74AUP1G373GW-Q100

絲?。?a target="_blank" title="Marking" href="/aw/marking.html">aW;Package:SC-88;Low-power D-type transparent latch; 3-state

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國(guó))有限公司

74AUP1G373GW-Q100H

Package:6-TSSOP,SC-88,SOT-363;包裝:管件 類(lèi)別:集成電路(IC) 鎖存器 描述:IC LATCH D-TYPE

Nexperia USA Inc.

Nexperia USA Inc.

74AUP1T34GW

Nexperia(安世)
SOT-353

Nexperia(安世)

相關(guān)企業(yè):深圳市金芯世紀(jì)電子有限公司

Nexperia(安世)

74AUP1T34GW

Nexperia(安世)
SOT-353

Nexperia(安世)

相關(guān)企業(yè):深圳市遠(yuǎn)進(jìn)半導(dǎo)體有限公司

Nexperia(安世)

技術(shù)參數(shù)

  • VCC (V):

    0.8?-?3.6

  • Logic switching levels:

    CMOS

  • Output drive capability (mA):

    1.9/-1.9

  • tpd (ns):

    8.5

  • fmax (MHz):

    1

  • Power dissipation considerations:

    ultra low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    264

  • Ψth(j-top) (K/W):

    38.6

  • Rth(j-c) (K/W):

    153

  • Package name:

    TSSOP6

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6-TSSOP
56200
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SSOP-6
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NA
500000
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6-TSSOP
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SOT3636(SC706)
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SOT363
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更多74AUP1G373GW-Q100供應(yīng)商 更新時(shí)間2025-7-31 10:03:00