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74ALVCH162827DGG

20-bit buffer/line driver, non-inverting,with 30ohm termination resistors (3-State)

DESCRIPTION The74ALVCH162827high-performanceCMOSdevicecombineslowstaticanddynamicpowerdissipationwithhighspeedandhighoutputdrive. FEATURES ?ComplieswithJEDECstandardno.8-1A. ?CMOSlowpowerconsumption ?DirectinterfacewithTTLlevels ?Currentdrive±12mAat3.0

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74ALVCH162827DGG

20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state

1Generaldescription The74ALVCH16282720-bitbuffersprovidehighperformancebusinterfacebuffering forwidedata/addresspathsorbusescarryingparity.TheyhaveNANDoutputenables (nOE1andnOE2)formaximumcontrolflexibility. The74ALVCH162827isdesignedwith30Ωseriesresisters

74ALVCH162827DGG

20-bit buffer/line driver; non-inverting; with 30 Ohm termination resistors; 3-state; ? CMOS low power consumption\n? MultiByte flow-through standard pin-out architecture\n? Low inductance multiple VCC and GND pins for minimum noise and ground bounce\n? Direct interface with TTL levels (2.7 V to 3.6 V)\n? Bus hold on data inputs\n? Current drive ± 12 mA at 3.0 V\n? Integrated 30 ? termination resistors\n? Complies with JEDEC standards:? JESD8-5 (2.3 V to 2.7 V)\n? JESD8B/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V\n? CDM JESD22-C101E exceeds 1000 V\n\n;

The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND output enables (nOE1 and nOE2) for maximum control flexibility.\n The 74ALVCH162827 is designed with 30 ? series resisters in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters.\n To ensure the high impedance state during power up or power down, nOEn should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.\n The 74ALVCH162827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.\n

74ALVCH162827DGG:1

Package：56-TFSOP（0.240"，6.10mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 緩沖器，驅(qū)動器，接收器，收發(fā)器 描述：IC BUF NON-INVERT 3.6V 56TSSOP

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74ALVCH162827DGGS

Package：56-TFSOP（0.240"，6.10mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 緩沖器，驅(qū)動器，接收器，收發(fā)器 描述：IC BUF NON-INVERT 3.6V 56TSSOP

ETC

74ALVCH162827DGGY

Package：56-TFSOP（0.240"，6.10mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 緩沖器，驅(qū)動器，接收器，收發(fā)器 描述：IC BUF NON-INVERT 3.6V 56TSSOP

ETC