首頁(yè)>74AHC1G02-Q100>規(guī)格書(shū)詳情
74AHC1G02-Q100中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠(chǎng)商型號(hào) |
74AHC1G02-Q100 |
| 功能描述 | 2-input NOR gate |
| 文件大小 |
232.68 Kbytes |
| 頁(yè)面數(shù)量 |
12 頁(yè) |
| 生產(chǎn)廠(chǎng)商 | NEXPERIA Nexperia B.V. All rights reserved |
| 中文名稱(chēng) | 安世 安世半導(dǎo)體(中國(guó))有限公司 |
| 網(wǎng)址 | |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-8-6 18:02:00 |
| 人工找貨 | 74AHC1G02-Q100價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
74AHC1G02-Q100規(guī)格書(shū)詳情
1. General description
The 74AHC1G02-Q100; 74AHCT1G02-Q100 is a single 2-input NOR gate. Inputs are overvoltage
tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
? Automotive product qualification in accordance with AEC-Q100 (Grade 1)
? Specified from -40 °C to +85 °C and from -40 °C to +125 °C
? Wide supply voltage range from 2.0 to 5.5 V
? Overvoltage tolerant inputs to 5.5 V
? High noise immunity
? CMOS low power dissipation
? Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
? Symmetrical output impedance
? Balanced propagation delays
? Input levels:
? For 74AHC1G02-Q100: CMOS level
? For 74AHCT1G02-Q100: TTL level
? ESD protection:
? HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
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21+ |
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23+ |
SOT353 |
25630 |
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25+ |
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7800 |
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12700 |
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25+ |
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54648 |
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DIODES/美臺(tái) |
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DIODES/美臺(tái) |
21+ |
SOT353 |
8080 |
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6000 |
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詢(xún)價(jià) |
