74ACT74屬于集成電路（IC）的觸發(fā)器。由意法半導(dǎo)體集團制造生產(chǎn)的74ACT74觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。

DESCRIPTION

The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND

CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.

A signal on the D INPUT is transferred to the Q and QOUTPUTS during the positive going

transition of the clock pulse.

CLEAR and PRESET are independent of the clock and accomplished by a low setting on the

appropriate input. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: fMAX= 250MHz (TYP.) at VCC= 5V

■ LOW POWER DISSIPATION: ICC= 4μA(MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS

VIH= 2V (MIN.), VIL = 0.8V (MAX.)

■ 50?TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL= 24mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ?tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74

■ IMPROVED LATCH-UP IMMUNITY