74ACT11074D屬于集成電路（IC）的觸發(fā)器。由美國德州儀器公司制造生產(chǎn)的74ACT11074D觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。

Inputs Are TTL-Voltage Compatible

Center-Pin VCC and GND Configurations to

Minimize High-Speed Switching Noise

EPIC (Enhanced-Performance Implanted

CMOS) 1-
m Process

500-mA Typical Latch-Up Immunity

at 125°C

Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline

(DB) Packages, and Standard Plastic

300-mil DIPs (N)

description

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)

or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR

are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs

on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed

without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from –40°C to 85°C.