General Description

The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

特性 Features

■ ICC reduced by 50

■ Ideal for addressable register applications

■ Clock enable for address and data synchronization applications

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

■ Outputs source/sink 24mA

■ See 273 for master reset version

■ See 373 for transparent latch version

■ See 374 for 3-STATE version

■ ACT377 has TTL-compatible inputs