74AC11244DBR屬于集成電路（IC）的緩沖器驅動器接收器收發(fā)器。由美國德州儀器公司制造生產的74AC11244DBR緩沖器，驅動器，接收器，收發(fā)器邏輯緩沖器、驅動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。

EPICE (Enhanced-Performance Implanted

CMOS ) 1-mm Process

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

Flow-Through Architecture Optimizes PCB

Layout

Center-Pin VCC and GND Pin

Configurations Minimize High-Speed

Switching Noise

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, and Standard Plastic DIPs (NT)

description

The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and

density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The

device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE) inputs.

When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 74AC11244 is characterized for operation from –40°C to 85°C.