General Description

The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

特性 Features

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

■ Buffered, asynchronous Master Reset

■ See ABT377 for clock enable version

■ See ABT373 for transparent latch version

■ See ABT374 for 3-STATE version

■ Output sink capability of 64 mA, source capability of 32 mA

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

■ Disable time less than enable time to avoid bus contention