描述 Description

The 5P49V5907 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

Programmable (OTP) memory or changed using I2C

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock? 5).

The frequencies are generated from a single reference clock

or crystal. Two select pins allow up to 4 different

configurations to be programmed and accessible using

processor GPIOs or bootstrapping. The different selections

may be used for different operating modes (full function,

partial function, partial power-down), regional standards (US,

Japan, Europe) or system production margin testing.

The device may be configured to use one of two I2C

addresses to allow multiple devices to be used in a system.

特性 Features

? Generates up to four independent output frequencies with a

total of 7 differential outputs and one reference output

? Supports multiple differential output I/O standards:

– Three universal outputs pairs with each configurable

as one differential output pair (LVDS, LVPECL or

regular HCSL) or two LVCMOS outputs. Frequency of

each output pair can be individually programmed

– Four copies of Low Power HCSL(LP-HCSL) outputs.

? Programmable frequency:

– See Output Features and Descriptions for details

? One reference LVCMOS output clock

? High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

? Four fractional output dividers (FODs)

? Independent Spread Spectrum capability from each

fractional output divider (FOD)

? Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

? I

2C serial programming interface

? Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz

to 200MHz

– Crystal frequency range: 8MHz to 40MHz

? Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LP-HCSL Clock Outputs – 1MHz to 200MHz

– Other Differential Clock Outputs – 1MHz to 350MHz

? Programmable loop bandwidth

? Programmable crystal load capacitance

? Power-down mode

? Mixed voltage operation:

– 1.8V core

– 1.8V VDDO for 4 LP-HCSL outputs

– 1.8V to 3.3V VDDO for other outputs

(3 programmable differential outputs and 1 reference

output)

– See Pin Descriptions for details

? Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)

? -40° to +85°C industrial temperature operation