描述 Description

General Description
The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.Asynchronous Inputs:
? LOW input to SD sets Q to HIGH level
? LOW input to CD sets Q to LOW level
? Clear and Set are independent of clock
? Simultaneous LOW on CD and SD makes both Q and Q HIGH

特性 Features

■ Guaranteed 4000V minimum ESD protection